A Multibank Memory-Based VLSI Architecture of DVB Symbol Deinterleaver

The main aim of this paper is an area efficient VLSI design of the symbol de interleaver based on a multibank single-port memory architecture. Data partitioning and access approach, the chance of memory conflict can be highly reduced such that only one additional FIFO (First In First Out)of length 31 is required

ØAddressed the lookahead DVB permutation address generator which can supply a valid address per cycle to avoid the extra use of a temporary buffer.

Ø30% savings of hardware cost can be achieved compared with the traditional approach

Ø The typical symbol-de interleaver design which consists of two ping-pong symbol buffers.

ØEach buffer can be realized by an on-chip SRAM block with Nmax cells and accessed under the control of the associated address generator

ØBy the proposed data partitioning and access approach, the chance of memory conflict can be highly reduced such that only one additional FIFO of length 31 is required.

Ø About 30% savings of hardware cost can be achieved compared with the traditional approach.

ØIntroduce a  look ahead DVB permutation address generator which can supply a valid address per cycle to avoid the extra use of a temporary buffer.

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