SEMINAR ON REDUCED INSTRUCTION SET COMPUTERS

Reduced instruction set computers aim for both simplicity in hardware and synergy between architectures and compilers. Optimizing compilers are used to compile programming languages down to instructions that are as unencumbered as micro instructions in a large virtual address space, and to make the instruction cycle time as fast as possible.

As circuit technologies reduce the relative cost of processing and memory, instruction sets that are too complex become a distinct liability to performance. The designers of reduced instruction set computers (RISCs) strive for both simplicity in hardware and synergy between architecture and compilers, in order to streamline processing as much as possible. Early experience indicates that RISCs can in fact run much faster than more conventionally designed machines.

In my lliew, the remaining technical difficulty is how to get good floating-point performance from RISCs. The

RISCs mentioned here have mediocre floating-point performance without special hardware assists. Another

issue is whether RISCs will provide the same advantages in the cost/performance factor for exploratory programming environments such as Lisp and Smalltalk. Initial experiments are promising.

I believe the split between architecture and implementation has caused architects to ignore the implementation consequences of architecture decisions, which has led to “good” architectures with disappointing implementations. Complex architecture requires lengthy. development cycles, and long development cycles using implementation technologies that routinely double in speed and capacity can potentially mean producing a computer in an antiquated technology. RISCs reduce this danger.

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